1. Field of the Invention
The present invention relates to a fringe field switching liquid crystal display (FFS-LCD) and a method for manufacturing the same, and more particularly, the present invention relates to an FFS-LCD in which a gate bus line is prevented from being damaged upon forming a counter electrode or a pixel electrode, and a method for manufacturing the same.
2. Description of the Related Art
Generally, the FFS-LCD is developed so as to increase an aperture ratio and a transmittance of an in-plane switching liquid crystal display (IPS-LCD), as described in Korean Patent Application No. 98-9243.
An FFS-LCD includes an upper substrate and a lower substrate which are separated from each other by a selected cell gap, a liquid crystal layer which is intervened between the upper and the lower substrates, and a counter electrode and a pixel electrode which are formed on an inner surface of the lower substrate. Each of the counter electrode and the pixel electrode is made of a transparent conductive material, and a distance between the counter electrode and the pixel electrode is set to be smaller than the selected cell gap. According to this, a fringe field is formed between and over the electrodes.
Referring to FIG. 1, there is shown a cross-sectional view of an FFS-LCD according to the convention art. A first indium tin oxide (ITO) is formed on a lower substrate 11. Then, a selected portion of the first ITO is patterned, thereby a counter electrode 12. After a metal film for a gate bus line is formed on the lower substrate 11 on which the counter electrode 12 is formed, a selected portion of the metal film is patterned thereby to form a gate bus line 13 and a common signal line (not shown). A gate insulating film 15 is deposited, to a predetermined thickness, on the lower substrate 11 on which the counter electrode 12, the gate bus line 13 and the common signal line are formed. An amorphous silicon layer and a doped silicon layer are sequentially deposited on the gate insulating film 15, and then, are patterned to include a selected portion of the gate bus line 13 thereby to form a channel layer 17 and an ohmic layer 18. Thereupon, after a metal film for a data bus line is formed on the gate insulating film 15 on which the channel layer 17 and the ohmic layer 18 are formed, by the fact that a predetermined portion of the metal film is patterned, source and drain electrodes 19a and 19b and a data bus line (not shown) are formed. A passivation film 20 is deposited on the gate insulating film 15 on which the source and drain electrodes 19a and 19b and the data bus line are formed, and then, is etched so that a selected portion of the drain electrode 19b is exposed. Thereafter, a second ITO is deposited on the passivation film 20 in a manner such that the second ITO is brought into contact with the exposed portion of the drain electrode 19b, and is patterned to have a comb teeth-shaped contour in a manner such that the second ITO is overlapped on the counter electrode 12, thereby to form a pixel electrode 21.
In the FFS-LCD of the convention art, constructed as mentioned above, the gate bus line 13 and the common signal line are formed on the same plane as the counter electrode 12, and specifically, the common signal line is brought into direct contact with the counter electrode 12. Therefore, aluminum (Al) having an etching speed which is similar to that of ITO used as a material for forming the counter electrode 12, cannot be properly used as a material for forming the gate bus line 13 and the common signal line. In other words, if the gate bus line 13 is formed of an aluminum layer, the counter electrode 12 is attacked by an etching solution for etching the gate bus line 13 when the gate bus line 13 is formed. Also, if an aluminum layer is direct-contacted with an ITO layer, a contact resistance is increased at a contact area.
To cope with this problems, in the conventional art, MoW which has a reduced reactivity with an ITO material, is mainly used for forming the gate bus line 13 and the common signal line. However, if a MoW layer is used as a material for forming the gate bus line and the common signal line, a line width should be increased since MoW has a signaling delay greater than that of a metal layer containing Al.
Moreover, since the gate insulating film 15 and the passivation film 20 are deposited between the counter electrode 12 and the pixel electrode 21, a distance between the electrodes 12 and 21 is lengthened. Due to this, an auxiliary capacitance is decreased.
Accordingly, the present invention has been made in an effort to solve the problems occurring in the related art, and an object of the present invention is to provide an FFS-LCD which has an increased aperture ratio, and a method for manufacturing the same.
Another object of the present invention is to provide an FFS-LCD in which a gate bus line is prevented from being damaged upon forming a counter electrode or a pixel electrode, and a method for manufacturing the same.
Still another object of the present invention is to provide an FFS-LCD which has an enhanced auxiliary capacitance, and a method for manufacturing the same.
According to one aspect of the present invention, there is provided an FFS-LCD comprising: a lower substrate; a plurality of gate bus lines extending along a selected direction on the lower substrate; a plurality of data bus lines disposed on the lower substrate in a manner such that they are crossed with the plurality of gate bus lines, for defining a unit pixel; a gate insulating film for insulating the gate bus lines and the data bus lines from each other; a thin film transistor located at a place where the gate bus lines and the data bus lines are crossed with each other; a pixel electrode formed on the gate insulating film, brought into contact with the thin film transistor and disposed in a space of the unit pixel; a counter electrode overlapped on the pixel electrode, the counter electrode cooperating with the pixel electrode for forming a fringe field which actuates all liquid crystal molecules existing on the pixel electrode and the counter electrode; and a passivation layer intervened between the pixel electrode and the counter electrode, wherein the pixel electrode and the counter electrode are made from a transparent conductive material and the plurality of gate bus lines are made as a metal film including aluminum.
According to another aspect of the present invention, there is provided an FFS-LCD comprising: a lower substrate; a plurality of gate bus lines extending along a selected direction on the lower substrate; a plurality of data bus lines disposed on the lower substrate in a manner such that they are crossed with the plurality of gate bus lines, for defining a unit pixel; a gate insulating film for insulating the gate bus lines and the data bus lines from each other; a thin film transistor located at a place where the gate bus lines and the data bus lines are crossed with each other; a pixel electrode formed on the gate insulating film, brought into contact with the thin film transistor and disposed in a space of the unit pixel; a counter electrode overlapped on the pixel electrode, the counter electrode cooperating with the pixel electrode for forming a fringe field which actuates all liquid crystal molecules existing on the pixel electrode and the counter electrode; and a passivation layer intervened between the pixel electrode and the counter electrode, wherein the gate bus lines include a pair of shielding sections which are located between the pixel electrode and the data bus lines, in a manner such that the pair of shielding sections extend parallel to the data bus lines, wherein the pixel electrode and the counter electrode are made from a transparent conductive material, and wherein the plurality of gate bus lines are made as a metal film including aluminum.
According to still another aspect of the present invention, there is provided a method for manufacturing an FFS-LCD comprising the steps of: forming a gate bus line and a shielding section on a predetermined region of a lower substrate; depositing a gate insulating film, an amorphous silicon layer and a doped semiconductor layer on the lower substrate; patterning selected portions of the doped semiconductor layer and the amorphous silicon layer and thereby forming an ohmic layer and a channel layer; forming a pixel electrode as a transparent conductive layer on the gate insulating film of one side of the channel layer; forming a source electrode and a drain electrode at both sides of the channel layer and a data bus line which is orthogonal to the gate bus line; forming a passivation film on the gate insulating film at a place where the data bus line and the pixel electrode are formed; etching the passivation film in a manner such that a predetermined portion of the gate bus line is exposed; and forming a counter electrode as a transparent conductive layer, on the passivation film in a manner such that the counter electrode is brought into contact with the exposed portion of the gate bus line, wherein each of the gate bus line and the shielding section are made as a metal film including aluminum.